一例将外部时钟引脚初始化为GPIO后，芯片无法连接。

[jinyi]

问题描述

• 某客户在BoardInit阶段将外部时钟引脚（如 OSC_IN/OSC_OUT）误配置为 GPIO，导致设备上电后 SWD 调试接口无法连接。

客户诉求

• 是否有可行的芯片恢复（解砖）方案？已尝试连接nRESET。

• 云途是否可提供防呆机制，避免类似误配再次导致调试口失联？

连接日志如下

Connecting ...
 - Connecting via USB to probe/ programmer device 0
 - Probe/ Programmer firmware: J-Link V9 compiled Dec 13 2022 11:14:50
 - Probe/ Programmer S/N: 25952305
 - Device "YTM32B1ME05" selected.
 - Target interface speed: 4000 kHz (Fixed)
 - VTarget = 3.288V
 - Found SW-DP with ID 0x6BA02477
 - DPv0 detected
 - CoreSight SoC-400 or earlier
 - Scanning AP map to find all available APs
 - AP[0]: Stopped AP scan as end of AP map seems to be reached
 - Iterating through AP map to find AHB-AP to use
 - Attach to CPU failed. Executing connect under reset.
 - DPv0 detected
 - CoreSight SoC-400 or earlier
 - Scanning AP map to find all available APs
 - AP[0]: Stopped AP scan as end of AP map seems to be reached
 - Iterating through AP map to find AHB-AP to use
 - Could not find core in Coresight setup
 - Found SW-DP with ID 0x6BA02477
 - Failed to power up DAP

[major]

如果引脚初始化在时钟初始化之后，可以尝试短接晶振的两个引脚，让MCU停在时钟初始化，此时用JLINK尝试连接，Halt并擦除，或者保持这个状态下进行重新烧录，注意短接之后进行一次重新上下电操作。
在异常状态直接短接或者复位应该无法直接恢复，必须要重新上下电。