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YTM32B1MD1中的ld档案修改问题?

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  • abcbillA 离线
    abcbillA 离线
    abcbill
    编写于 最后由 编辑
    #1

    /*

    • Copyright 2020-2025 Yuntu Microelectronics Co., Ltd.
    • All rights reserved.
    • SPDX-License-Identifier: BSD-3-Clause
    • @file yt_linker.ld
    • @brief

    */

    /* MEMORY MAP /
    MEMORY
    {
    IVT (RX) : ORIGIN = 0x0, LENGTH = 0x400
    TEXT (RX) : ORIGIN = 0x400, LENGTH = 0x7bc00
    DTC (RX) : ORIGIN = 0x7c000, LENGTH = 0x1000
    DTC_BACKUP (RX) : ORIGIN = 0x7d000, LENGTH = 0x1000
    INF (RX) : ORIGIN = 0x7e000, LENGTH = 0x1000
    INF_BACKUP (RX) : ORIGIN = 0x7f000, LENGTH = 0x1000
    IVT_RAM (RW) : ORIGIN = 0x1fff8000, LENGTH = 0x400
    STACK (RW) : ORIGIN = 0x20007c00, LENGTH = 0x400
    RAM (RW) : ORIGIN = 0x1fff8400, LENGTH = 0xf800
    }
    /     SECTIONS */
    SECTIONS
    {
    .IVT : {

        IVT_start = .;
    isr_vector_region_start = .;
    KEEP(*(.isr_vector))
    isr_vector_region_end = .;
    
    IVT_end = .;
} > IVT




.TEXT  : {
    
    TEXT_start = .;
    rodata_region_start = .;
    *(.rodata)
    *(.rodata*)
    rodata_region_end = .;
    
    text_region_start = .;
    *(.text)
    *(.text*)
    text_region_end = .;
    
    TEXT_end = .;
} > TEXT




.ARM  : {
    
    ARM_start = .;
    ARM.exidx_region_start = .;
    *(.ARM.exidx)
    *(.ARM.exidx*)
    ARM.exidx_region_end = .;
    
    ARM_end = .;
} > TEXT




CODE_RAM_rom_start_not_align = .;
CODE_RAM_rom_start = CODE_RAM_rom_start_not_align + (CODE_RAM_rom_start_not_align % 4);

CODE_RAM_rom_end = CODE_RAM_rom_start + CODE_RAM_ram_end - CODE_RAM_ram_start;



DATA_RAM_rom_start_not_align = CODE_RAM_rom_end;
DATA_RAM_rom_start = DATA_RAM_rom_start_not_align + (DATA_RAM_rom_start_not_align % 4);

DATA_RAM_rom_end = DATA_RAM_rom_start + DATA_RAM_ram_end - DATA_RAM_ram_start;



.DTC  (NOLOAD): {
    
    . = ALIGN(4096);
    DTC_start = .;
    . += 4096;
    . = ALIGN(4096);
    DTC_end = .;
} > DTC




.DTC_BACKUP  (NOLOAD): {
    
    . = ALIGN(4096);
    DTC_BACKUP_start = .;
    . += 4096;
    . = ALIGN(4096);
    DTC_BACKUP_end = .;
} > DTC_BACKUP




.INF  (NOLOAD): {
    
    . = ALIGN(4096);
    INF_start = .;
    . += 4096;
    . = ALIGN(4096);
    INF_end = .;
} > INF




.INF_BACKUP  (NOLOAD): {
    
    . = ALIGN(4096);
    INF_BACKUP_start = .;
    . += 4096;
    . = ALIGN(4096);
    INF_BACKUP_end = .;
} > INF_BACKUP




.IVT_RAM  : {
    
    . = ALIGN(1024);
    IVT_RAM_start = .;
    . += 0X400;
    IVT_RAM_end = .;
} > IVT_RAM




.STACK  : {
    
    STACK_start = .;
    . += 1024;
    STACK_end = .;
} > STACK




.BSS  (NOLOAD): {
    
    BSS_start = .;
    bss_region_start = .;
    *(.bss)
    *(.bss*)
    bss_region_end = .;
    
    BSS_end = .;
} > RAM




.CODE_RAM  : AT(CODE_RAM_rom_start) {
    
    . = ALIGN(4);
    CODE_RAM_ram_start = .;
    CODE_RAM_start = .;
    code_ram_region_start = .;
    *(.code_ram)
    code_ram_region_end = .;
    
    CODE_RAM_end = .;
    CODE_RAM_ram_end = .;
} > RAM


ASSERT((CODE_RAM_ram_end - CODE_RAM_ram_start) == (CODE_RAM_rom_end - CODE_RAM_rom_start), "Copy Section CODE_RAM Size non-aligned")


.DATA_RAM  : AT(DATA_RAM_rom_start) {
    
    DATA_RAM_ram_start = .;
    DATA_RAM_start = .;
    data_region_start = .;
    *(.data)
    *(.data*)
    data_region_end = .;
    
    DATA_RAM_end = .;
    DATA_RAM_ram_end = .;
} > RAM


ASSERT((DATA_RAM_ram_end - DATA_RAM_ram_start) == (DATA_RAM_rom_end - DATA_RAM_rom_start), "Copy Section DATA_RAM Size non-aligned")


IVT_memory_start = ORIGIN(IVT);
IVT_memory_end = ORIGIN(IVT) + LENGTH(IVT);
IVT_memory_size = LENGTH(IVT);
TEXT_memory_start = ORIGIN(TEXT);
TEXT_memory_end = ORIGIN(TEXT) + LENGTH(TEXT);
TEXT_memory_size = LENGTH(TEXT);
DTC_memory_start = ORIGIN(DTC);
DTC_memory_end = ORIGIN(DTC) + LENGTH(DTC);
DTC_memory_size = LENGTH(DTC);
DTC_BACKUP_memory_start = ORIGIN(DTC_BACKUP);
DTC_BACKUP_memory_end = ORIGIN(DTC_BACKUP) + LENGTH(DTC_BACKUP);
DTC_BACKUP_memory_size = LENGTH(DTC_BACKUP);
INF_memory_start = ORIGIN(INF);
INF_memory_end = ORIGIN(INF) + LENGTH(INF);
INF_memory_size = LENGTH(INF);
INF_BACKUP_memory_start = ORIGIN(INF_BACKUP);
INF_BACKUP_memory_end = ORIGIN(INF_BACKUP) + LENGTH(INF_BACKUP);
INF_BACKUP_memory_size = LENGTH(INF_BACKUP);
IVT_RAM_memory_start = ORIGIN(IVT_RAM);
IVT_RAM_memory_end = ORIGIN(IVT_RAM) + LENGTH(IVT_RAM);
IVT_RAM_memory_size = LENGTH(IVT_RAM);
STACK_memory_start = ORIGIN(STACK);
STACK_memory_end = ORIGIN(STACK) + LENGTH(STACK);
STACK_memory_size = LENGTH(STACK);
RAM_memory_start = ORIGIN(RAM);
RAM_memory_end = ORIGIN(RAM) + LENGTH(RAM);
RAM_memory_size = LENGTH(RAM);

    }
    上面是项目中的ld檔,修改完后SPI的初始程序(下面所示)会一直在下面循环出不来(修改前是没问题的),请问有可能是什么原因呢?会不会是.bss档没清0呢?请问sample code清0的程序在那呢?
    while (spiState->rxCount != (uint16_t)0)
    {
    /* Read the last word from the RX FIFO */
    if (SPI_GetStatusFlag(base, SPI_RX_DATA_FLAG))
    {
    SPI_DRV_ReadRXBuffer(instance);
    }
    }

    1 条回复 最后回复
    0
    • swustS 离线
      swustS 离线
      swust YunTu
      编写于 最后由 编辑
      #2

      看下map文件，检查下text是不是溢出了

      1 条回复 最后回复
      0
      • abcbillA 离线
        abcbillA 离线
        abcbill
        编写于 最后由 编辑
        #3

        map 里显示：
        • TEXT：Origin 0x00000400，Length 0x0007BC00
        → 结束地址 = 0x0007C000
        map 里显示：
        • .TEXT output section 大小 0x7AC8，从 0x00000400 开始，到 0x00007EC8
        • .ARM output section 在 0x00007EC8，大小 0x8，到 0x00007ED0
        • .CODE_RAM 的 load address = 0x00007ED0
        • .DATA_RAM 的 load address = 0x00007FA8
        • DATA_RAM_rom_end = 0x000082C
        • Flash 实际用到大约 0x000082C9

        1 条回复 最后回复
        0
        • swustS 离线
          swustS 离线
          swust YunTu
          编写于 最后由 编辑
          #4

          这说明没溢出，那就看一下spiState被编到了哪个位置，如果在.code_ram 或 .data_ram，手动改一下Raminit1.c。

          1 条回复 最后回复
          0
          • abcbillA 离线
            abcbillA 离线
            abcbill
            编写于 最后由 编辑
            #5

            .bss.g_spiStatePtr
            0x1fff8c20 0x10 libGENERATED_SDK_TARGET.a(spi_shared_function.c.o)
            0x1fff8c20 g_spiStatePtr
            看起来是在.bss
            但奇怪的是我用原本的ld檔就不会出事,底下为原本的ld檔
            /*

            • Copyright 2020-2025 Yuntu Microelectronics Co., Ltd.
            • All rights reserved.
            • SPDX-License-Identifier: BSD-3-Clause
            • @file yt_linker.ld
            • @brief

            */

            /* MEMORY MAP /
            MEMORY
            {
            IVT (RX) : ORIGIN = 0x0, LENGTH = 0x400
            BOOT (RX) : ORIGIN = 0x400, LENGTH = 0x7c00
            IVT_RAM (RW) : ORIGIN = 0x1fff8000, LENGTH = 0x400
            STACK (RW) : ORIGIN = 0x20007c00, LENGTH = 0x400
            RAM (RW) : ORIGIN = 0x1fff8400, LENGTH = 0xf800
            }
            /             SECTIONS */
            SECTIONS
            {
            .IVT : {

                IVT_start = .;
    isr_vector_region_start = .;
    KEEP(*(.isr_vector))
    isr_vector_region_end = .;
    
    IVT_end = .;
} > IVT




.TEXT  : {
    
    TEXT_start = .;
    rodata_region_start = .;
    *(.rodata)
    *(.rodata*)
    rodata_region_end = .;
    
    text_region_start = .;
    *(.text)
    *(.text*)
    text_region_end = .;
    
    TEXT_end = .;
} > BOOT




.ARM  : {
    
    ARM_start = .;
    ARM.exidx_region_start = .;
    *(.ARM.exidx)
    *(.ARM.exidx*)
    ARM.exidx_region_end = .;
    
    ARM_end = .;
} > BOOT




CODE_RAM_rom_start_not_align = .;
CODE_RAM_rom_start = CODE_RAM_rom_start_not_align + (CODE_RAM_rom_start_not_align % 4);

CODE_RAM_rom_end = CODE_RAM_rom_start + CODE_RAM_ram_end - CODE_RAM_ram_start;



DATA_RAM_rom_start_not_align = CODE_RAM_rom_end;
DATA_RAM_rom_start = DATA_RAM_rom_start_not_align + (DATA_RAM_rom_start_not_align % 4);

DATA_RAM_rom_end = DATA_RAM_rom_start + DATA_RAM_ram_end - DATA_RAM_ram_start;



.IVT_RAM  : {
    
    . = ALIGN(1024);
    IVT_RAM_start = .;
    . += 0X400;
    IVT_RAM_end = .;
} > IVT_RAM




.STACK  : {
    
    STACK_start = .;
    . += 1024;
    STACK_end = .;
} > STACK




.BSS  (NOLOAD): {
    
    BSS_start = .;
    bss_region_start = .;
    *(.bss)
    *(.bss*)
    bss_region_end = .;
    
    BSS_end = .;
} > RAM




.CODE_RAM  : AT(CODE_RAM_rom_start) {
    
    . = ALIGN(4);
    CODE_RAM_ram_start = .;
    CODE_RAM_start = .;
    code_ram_region_start = .;
    *(.code_ram)
    code_ram_region_end = .;
    
    CODE_RAM_end = .;
    CODE_RAM_ram_end = .;
} > RAM


ASSERT((CODE_RAM_ram_end - CODE_RAM_ram_start) == (CODE_RAM_rom_end - CODE_RAM_rom_start), "Copy Section CODE_RAM Size non-aligned")


.DATA_RAM  : AT(DATA_RAM_rom_start) {
    
    DATA_RAM_ram_start = .;
    DATA_RAM_start = .;
    data_region_start = .;
    *(.data)
    *(.data*)
    data_region_end = .;
    
    DATA_RAM_end = .;
    DATA_RAM_ram_end = .;
} > RAM


ASSERT((DATA_RAM_ram_end - DATA_RAM_ram_start) == (DATA_RAM_rom_end - DATA_RAM_rom_start), "Copy Section DATA_RAM Size non-aligned")


IVT_memory_start = ORIGIN(IVT);
IVT_memory_end = ORIGIN(IVT) + LENGTH(IVT);
IVT_memory_size = LENGTH(IVT);
BOOT_memory_start = ORIGIN(BOOT);
BOOT_memory_end = ORIGIN(BOOT) + LENGTH(BOOT);
BOOT_memory_size = LENGTH(BOOT);
IVT_RAM_memory_start = ORIGIN(IVT_RAM);
IVT_RAM_memory_end = ORIGIN(IVT_RAM) + LENGTH(IVT_RAM);
IVT_RAM_memory_size = LENGTH(IVT_RAM);
STACK_memory_start = ORIGIN(STACK);
STACK_memory_end = ORIGIN(STACK) + LENGTH(STACK);
STACK_memory_size = LENGTH(STACK);
RAM_memory_start = ORIGIN(RAM);
RAM_memory_end = ORIGIN(RAM) + LENGTH(RAM);
RAM_memory_size = LENGTH(RAM);

            }

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