<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:atom="http://www.w3.org/2005/Atom" version="2.0"><channel><title><![CDATA[MD2 etmr0配置成输出比较异常问题]]></title><description><![CDATA[<p dir="auto">MD2 etmr0一共配置了6个通道的输出比较，初始化时给一个时间去触发中断，进入中断后安排一段时间后再进入中断，如此循环，测试发现一共6个通道，有2个通道CH0,CH1正常，有4个通道CH4,CH5,CH6,CH7会停止进中断，同样的代码移植到ME0里没有问题!```<br />
code_text</p>
<pre><code class="language-![ScreenShot_2026-07-01_170000_330.png](https://yt-static-main.oss-cn-shanghai.aliyuncs.com/nodebb/1763/0008f3c2-8ba5-4084-8ea8-4d3ce4510242.png)"></code></pre>
]]></description><link>https://forum.ytmicro.com/topic/2078/md2-etmr0配置成输出比较异常问题</link><generator>RSS for Node</generator><lastBuildDate>Wed, 01 Jul 2026 19:06:05 GMT</lastBuildDate><atom:link href="https://forum.ytmicro.com/topic/2078.rss" rel="self" type="application/rss+xml"/><pubDate>Wed, 01 Jul 2026 09:05:03 GMT</pubDate><ttl>60</ttl><item><title><![CDATA[Reply to MD2 etmr0配置成输出比较异常问题 on Wed, 01 Jul 2026 09:08:37 GMT]]></title><description><![CDATA[<p dir="auto">初始化：<br />
eTMR_DRV_Deinit(eTMR_INST_oc);<br />
eTMR_DRV_Init(eTMR_INST_oc, &amp;eTMR_Config, &amp;etmrState_oc);<br />
eTMR_DRV_InitOutputCompare(eTMR_INST_oc, &amp;eTMR_OutputCmpParamConfig);<br />
INT_SYS_InstallHandler(eTMR0_Ch0_Ch1_IRQn, eTMR0_Ch0_Ch1_IRQHandler_OutputCompare, NULL);<br />
INT_SYS_InstallHandler(eTMR0_Ch4_Ch5_IRQn, eTMR0_Ch4_Ch5_IRQHandler_OutputCompare, NULL);<br />
INT_SYS_InstallHandler(eTMR0_Ch6_Ch7_IRQn, eTMR0_Ch6_Ch7_IRQHandler_OutputCompare, NULL);</p>
<pre><code>/* set priority */
INT_SYS_SetPriority(eTMR0_Ch0_Ch1_IRQn,2);
INT_SYS_SetPriority(eTMR0_Ch4_Ch5_IRQn,2);
INT_SYS_SetPriority(eTMR0_Ch6_Ch7_IRQn,2);

/* Enable IRQ in NVIC level */
INT_SYS_EnableIRQ(eTMR0_Ch0_Ch1_IRQn);
INT_SYS_EnableIRQ(eTMR0_Ch4_Ch5_IRQn);
INT_SYS_EnableIRQ(eTMR0_Ch6_Ch7_IRQn);

eTMR0-&gt;INTE |= eTMR_INTE_CH0IE_MASK;
eTMR0-&gt;INTE |= eTMR_INTE_CH1IE_MASK;
eTMR0-&gt;INTE |= eTMR_INTE_CH4IE_MASK;
eTMR0-&gt;INTE |= eTMR_INTE_CH5IE_MASK;
eTMR0-&gt;INTE |= eTMR_INTE_CH6IE_MASK;
eTMR0-&gt;INTE |= eTMR_INTE_CH7IE_MASK;
eTMR_DRV_Enable(eTMR_INST_oc);
</code></pre>
<p dir="auto">中断：<br />
uint32_t statusFlags = 0U;<br />
statusFlags = g_etmrBase[eTMR0_INST_PWM]-&gt;STS;                              //read channel status flags.<br />
if( (statusFlags&amp;eTMR_STS_CH6F_MASK) == eTMR_STS_CH6F_MASK )                //channel2<br />
{<br />
g_etmrBase[eTMR0_INST_PWM]-&gt;STS = eTMR_STS_CH6F_MASK;</p>
<pre><code>	//g_etmrBase[eTMR0_INST_PWM]-&gt;SYNC |= eTMR_SYNC_LDOK_MASK|eTMR_SYNC_SWTRIG_MASK;
    //点火2
    OC_IGN2_OnInterrupt(g_etmrBase[eTMR0_INST_PWM]-&gt;CNT);
}
if( (statusFlags&amp;eTMR_STS_CH7F_MASK) == eTMR_STS_CH7F_MASK )
{
	g_etmrBase[eTMR0_INST_PWM]-&gt;STS = eTMR_STS_CH7F_MASK;

	//g_etmrBase[eTMR0_INST_PWM]-&gt;SYNC |= eTMR_SYNC_LDOK_MASK|eTMR_SYNC_SWTRIG_MASK;
	//点火1
    OC_IGN_OnInterrupt(g_etmrBase[eTMR0_INST_PWM]-&gt;CNT);
}
</code></pre>
<p dir="auto">void OC_IGN_OnInterrupt(uint32_t c_val)//ch7<br />
{<br />
switch(MCU_PWMSignal_7_PD10_st)<br />
{<br />
case 0:<br />
break;<br />
case 1:<br />
dri_FUN_oc_ch7_Trig(500,1);<br />
MCU_PWMSignal_7_PD10_st = 2;<br />
break;<br />
case 2:<br />
dri_FUN_oc_ch7_Trig(500,0);<br />
MCU_PWMSignal_7_PD10_st = 1;<br />
break;<br />
default:<br />
break;<br />
}<br />
}<br />
触发：<br />
void dri_FUN_oc_ch0_Trig(uint32_t time, uint32_t ST)<br />
{<br />
#if (M_OC_Mode == M_OC_out_PWM_Mode)<br />
uint32_t val0_set_v;<br />
eTMR_Type * const etmrBase = g_etmrBase[eTMR_INST_oc];<br />
eTMR_DRV_ClearLdok(eTMR_INST_oc);<br />
val0_set_v = etmrBase-&gt;CNT + time;<br />
if( val0_set_v &gt;= (etmrBase-&gt;MOD+1) )<br />
{<br />
val0_set_v = val0_set_v - (etmrBase-&gt;MOD+1);           //correct new val0<br />
}<br />
eTMR_DRV_UpdateOutputCompareChannel(eTMR_INST_oc,M_MCU_ocSignal_0_ch,val0_set_v,val0_set_v,ST,ST,1);</p>
<p dir="auto">#endif<br />
}</p>
]]></description><link>https://forum.ytmicro.com/post/8997</link><guid isPermaLink="true">https://forum.ytmicro.com/post/8997</guid><dc:creator><![CDATA[xufengkun]]></dc:creator><pubDate>Wed, 01 Jul 2026 09:08:37 GMT</pubDate></item></channel></rss>